The PCB in a mobile phone is only as thick as a coin, so how can it hold the "entire universe"?

The answer lies in the layered design of multilayer PCBs. From routers costing hundreds of dollars to servers costing tens of thousands of dollars, from Bluetooth headsets to automotive electronic control systems, multilayer PCBs use "three-dimensional wiring" to break through spatial limitations and simplify complex circuits.

Multilayer PCB

Definition: A rigid or rigid-flex circuit board constructed by laminating two or more layers of conductive copper foil with a dielectric (insulating layer) and laminating, interconnected by vias.

Typical range: 4–40 layers (4/6/8/10/12 layers are common). More layers provide greater routing freedom, power supply, and shielding capabilities, but also increase cost and manufacturing difficulty.

Key elements: Signal layer, ground plane, power plane, inner layer signal layer, dielectric (prepreg/core), and vias (through hole, blind/buried via, micro blind via).

Why Choose a Multilayer PCB?

High-Density Routing: Addresses BGA/high-pin-density devices, alleviating routing congestion and via stacking.
High Speed and Impedance Control: Constructs a "signal layer + reference plane" transmission line structure to achieve controlled impedances, such as 50 Ω single-ended and 90/100 Ω differential.
Electromagnetic Compatibility (EMC/EMI): A continuous ground plane provides a return path and shields sensitive networks, reducing radiated and conducted interference.
Power Consumption and Power Integrity (PI): Proximally located power/ground planes form an equivalent capacitance within the board, working in conjunction with decoupling networks to smooth power supply noise.
Size and Structure: Using "three-dimensional routing" instead of "planar expansion" significantly reduces board area and thickness, enabling portable and thin designs.

Typical Applications: Smartphones/tablets, routers and switches, automotive ECUs, industrial control, medical equipment, servers and storage, AR/VR, IoT modules, etc.

Functions of Each Layer in a Multilayer PCB

Signal Layer
Function: Data/Control/Clock/High-Speed Differential
Key Points: Keep high-frequency components as close to a complete ground plane as possible; prioritize critical nets on inner layers; minimize reference plane changes.
Ground Plane (GND)
Function: Provide the shortest return path and shielding.
Key Points: Avoid cuts or large openings; stitch vias across areas; maintain continuity and integrity in sensitive areas.
Power Plane (PWR)
Function: Provide power to different voltage domains.
Key Points: Clearly partition power supply areas; tightly couple with the ground plane (thin dielectric) to increase internal capacitance; thicken or use copper in high-current areas.
Mechanical Layer
Function: Provides board frame, mounting holes, chamfers, tolerances, and keep-out areas.
Key Points: Manufacturing is based on the mechanical layer; clearly define keep-outs around antennas, connectors, and heat sinks.
Silkscreen Layer
Function: Provides tag numbers, polarity, orientation, and process identification.

Key Points: Avoid overlaying pads; fonts and line widths must meet factory minimum readability specifications.

Key Design Points for Multilayer PCBs

Impedance and Signal Integrity (SI)
Specifications: 50 Ω single-ended, 90/100 Ω differential (USB 3.x, PCIe, Ethernet, etc.). Typical tolerances are ±10% (±8%/±5% at the high end).
Recommendations:
Trace routing should preferably be located on layers adjacent to the reference plane. Outer microstrip and inner stripline should be selected to match dielectric and copper thicknesses.
Differential pairs: Equal length, equal coupling, and equal references. Minimize the number of vias and asymmetry. Avoid cross-plane splits.

Length matching: Follow protocol specifications (e.g., DDR and PCIe requirements). Trace bends should preferably be 45° or circular.

Return Current Paths and EMC

Maintain a continuous reference plane; use stitching vias to bridge return currents at crossovers.

High-frequency/fast-edge signals should not be split across ground planes. If crossovers are necessary, add dense stitching vias nearby. Sensitive analog areas should be partitioned from strong interference sources (motor drive, DC-DC) and isolated with ground planes.

Power Integrity (PI) and Decoupling

The power plane and ground plane should be close together, and the dielectric should be as thin as possible to maximize plane capacitance.
Decoupling Strategy: Use parallel ladders of large, medium, and small (10 μF/1 μF/0.1 μF/0.01 μF); place them as close to the pins as possible, prioritizing short loops and direct via connections.

Wide high-current paths, add copper, and use multiple vias; use copper strips/heat sinks as needed.

Vias and Interconnects

Through vias: Versatile and low-cost; be aware of the impact of via stubs on high-speed connections.
Blind/buried vias and microvias (laser microvias ≤ 0.1–0.15 mm): Suitable for BGA fan-outs and HDI.

Backdrilling: Remove via stubs from high-speed networks to reduce reflections and resonance. Recommendations: Minimize vias for high-speed networks; add pairs of stitching vias at reference plane transitions.

Thermal Design

Incorporate a large copper surface and thermal via arrays (via-in-pad/near-near vias) on the bottom of power devices.
Equalize copper placement and fill copper depressions (thieving) to improve press-fit and thermal consistency.

Thermal relief pads (thermal relief) balance solderability and heat dissipation.

Manufacturability (DFM/DFA)

Avoid extremely thin isolated copper and sharp corners; maintain a manufacturable solder bridge width.
BGA via solution: Solder mask capping, plugging, filling, and copper surface smoothing options are available as needed.

Panelization: Define the processing edge, process holes, fiducials, and panel separation method (V-cut/stamp hole) in advance.

Multilayer PCB Material and Process Selection

Base Material: FR-4 (most applications), High-Tg FR-4 (high temperature), High-speed/High-frequency materials (low Dk/Df, such as mixed-press Rogers + FR-4).
Thickness and Copper Thickness: Common finished product thicknesses are 0.8/1.0/1.2/1.6 mm; 1 oz copper is standard, 2–3 oz is acceptable for power/high current applications.
Dielectric Parameters: Dk/Df and thickness determine impedance; communicate with the manufacturer to specify the dielectric type and thickness tolerance.
Surface Finish: ENIG (Immersion Gold Ingot; smooth, corrosion-resistant, suitable for fine pitch/BGA), HASL/Lead-Free HASL (economical), Immersion Silver/Immersion Tin (excellent solderability).
Solder Mask Color: Green (mature process, good contrast), black/white/blue, etc., require attention to solderability and contrast. Process Capabilities (subject to actual factory capabilities):
Minimum Line/Space: Conventional 4/4 mil; HDI can reach 3/3 or smaller.
Finished Mechanical Via Diameter: Commonly ≥0.2–0.3 mm; Micro Blind Via ≤0.1–0.15 mm.

Via Aspect Ratio: Typical for through-holes: ≤8–10:1; higher requirements require reliability assessment.

Multilayer PCB Quality and Testing

Standards and Grades: IPC-6012 Class 2 (General Purpose), Class 3 (High Reliability/Automotive); UL-certified materials and flame retardant grades (e.g., UL94 V-0) available.
Process Inspection: AOI (internal and external layers), flying probe/fixture electrical testing, X-ray (BGA/buried vias), visual and dimensional inspection.

Reliability: Thermal cycling, damp heat, CAF evaluation (for high-voltage and fine-pitch applications), and micro Blind Via stacking/staggering verification (refer to IPC-2226).

For multilayer board stackup recommendations, controlled impedance calculations, and a sample quote for your project, please contact PCBAMake's technical and sales team. We support prototypes from 2–40 layers to low-volume production, and provide design for manufacturability (DFM) reviews and production ramp-up support.